The Linux Plumbers 2019 RISC-V MC will continue the trend established in 2018  to address different relevant problems in RISC-V Linux land.
The overall progress in RISC-V software ecosystem since last year has been really impressive. To continue the similar growth, RISC-V track at Plumbers will focus on finding solutions and discussing ideas that require kernel changes. This will also result in a significant increase in active developer participation in code review/patch submissions which will definitely lead to a better and more stable kernel for RISC-V.
RISC-V Platform Specification Progress, including some extensions such as power management - Palmer Dabbelt
Fixing the Linux boot process in RISC-V (RISC-V now has better support for open source boot loaders like U-Boot and coreboot compared to last year. As a result of this developers can use the same boot loaders to boot Linux on RISC-V as they do in other architectures, but there's more work to be done) - Atish Patra
RISC-V hypervisor emulation  - Alistair Francis
RISC-V hypervisor implementation - Anup Patel
NOMMU Linux for RISC-V - Damien Le Moal
More to be added based on CfP for this microconference
If you are interested in participating in this microconference and have topics to propose, please use the CfP process. More topics will be added based on CfP for this microconference.
Atish Patra (email@example.com) or Palmer Dabbelt (firstname.lastname@example.org)
The RISC-V UNIX-Class platform specification working group started in May and aims to have a first release by the end of the year. This talk will discuss where we are and where we're going.
RISC-V now has better support for open source boot loaders like U-Boot and coreboot compared to last year. As a result of this developers can use the same boot loaders to boot Linux on RISC-V as they do in other architectures, but there's more work to be done. We will discuss the current state of the boot flow and pending issues.
IOMMU is a very popluar equipment for both embed and server virtualization area. In the topic we'll focus on embed area and shared virtual address.
Firstly, we'll talk about the value of IOMMU for the embed system and what the benefit we could get from IOMMU in our cost-down embed system.
Secondly, Guo will share the experience on the IOMMU implementation, eg: How to keep the same asid with...
RISC-V trace spec draft have defined some trace format, we'll share our implementation of linux perf trace based on the spec. How to deal with SMP perf issues, how to verify our design in qemu, demonstrate a demo of perf trace with riscv-qemu.
Lastly, let's discuss perf issues from PMU to trace, any riscv perf topic.
The current main uses cases of RISC V center on embedded uses and small configurations. However, RISC V seems to be also a useful platform to do High Performance Computing and may be able to deliver custom solutions that can go well beyond what the traditional processor vendors can offer. There are already efforts underway to use ARM for that purpose but those approaches are constrained by...
The RISC-V hypervisor extension is carefully designed to be compliant with both Type-1 and Type-2 hypervisors. We have ported Xvisor (Type-1) and KVM (Type-2) for RISC-V architecture. In this session, we share our experience porting these hypervisors and also discuss future work on RISC-V hypervisors.
This presentation discusses the work done to add the RISC-V Hypervisor Extension support to QEMU. This allows everyone to use QEMU as a development platform for porting Hypervisors to RISC-V. This can be seen by the recent effort to port KVM to RISC-V.
This presentation will discuss how the RISC-V Hypervisor extension works and how it is different to other common architectures Hypervisor...
What's it going to take to allow us to make the benefits of the RISC-V
architecture available in centralized computing systems? Are there some
things we need to be working on right now to pave the way for future
success here? How can the state of the ARM architecture help us
understand this problem?
This presentation will explore the technical decisions made in designing
a data-center scale...
This presentation will discuss the work ongoing to implement Linux kernel
support for RISCV hardware lacking a memory management unit (MMU). A side effect
of this work is also the ability to execute the kernel directly in M-Mode and
how this is implemented while keeping most of the architecture code unmodified.
The presentation will include examples of testing environment builds, discuss
Compared to VM, container technology has been always argued for the security. We might need to discuss how to fit current container implementation into RISC-V arch in such a area. And RISC-V has not had any particular hardware considerations like Intel SGX and even AMD, however we can go far as we can and get some feedback to RISC-V foundation.