13-15 November 2018
America/Vancouver timezone

Enhancing perf to export processor hazard information

15 Nov 2018, 11:45
Pavillion-Ballroom-AB (Sheraton Vancouver Wall Center)


Sheraton Vancouver Wall Center

Refereed talk LPC Main Track


Mr. Madhavan Srinivasan (IBM Linux Technology Center)


Most modern microprocessors employ complex instruction execution pipelines such that many instructions can be 'in flight' at any given point in time. The efficiency of this pipelining is typically measured in how many instructions get completed per CPU cycle and the metric gets variously called as Instructions Per Cycle (IPC) or the inverse metric Cycles Per Instruction (CPI). Various factors affect this metric and hazards are the primary among them. Different types of hazards exist - Data hazards, Structural hazards and Control hazards. Data hazard is the case where data dependencies exist between instructions in different stages in the pipeline. Structural hazard is when the same processor hardware is needed by more than one instruction in flight at the same time. Control hazards are more the branch misprediction kinds. Information about these hazards are critical towards analyzing performance issues and also to tune software to overcome such issues. Modern processors export such hazard data in Performance Monitoring Unit (PMU) registers. In this talk, we propose an arch neutral extension to perf to export the hazard data presented in different ways by different architectures. We also present how this extension has been applied to the IBM Power processor, the APIs and example output.

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Primary author

Mr. Madhavan Srinivasan (IBM Linux Technology Center)

Presentation Materials

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