20-24 September 2021
US/Pacific timezone

Puzzle for RISC-V ifunc

21 Sep 2021, 10:00
30m
Microconference3/Virtual-Room (LPC Virtual)

Microconference3/Virtual-Room

LPC Virtual

150
RISC-V MC RISC-V MC

Speakers

Kito Cheng (SiFive) Palmer Dabbelt (Google)

Description

ifunc is a widely used mechnish for specialized those performance
critical functions in glibc, like memcpy, strcmp and strlen.
It’s not used in upstream glibc for RISC-V yet, but with several new
extensions becoming ratified soon, users will desire to have
vector-optimized routines to boost their program.
It’s a generic infrastructure for GNU toolchain, so we don’t need too
much work to enable that in theory, but the real world isn’t so
wonderful…

Here is the list of the puzzle for the RISC-V ifunc, some is there and
some is missing:
- Relocation for ifunc.
- https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/131
- Mapping symbol.
- https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/196
- New asm directive to enable/disable any extension in specific code
region (like .option rvc/.option norvc, but more generic one.)
- https://github.com/riscv-non-isa/riscv-asm-manual/pull/67
- New function target attribute for C/C++
- e.g. int sse3_func (void) attribute ((target ("sse3")));
- hwcap and hwcap2

Most items are toolchain stuff, but last item for hwcap, it should
coordinate between glibc and linux kernel to implement a new mechanism
to discover the machine capability.

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Primary authors

Kito Cheng (SiFive) Palmer Dabbelt (Google)

Presentation Materials

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