20-24 September 2021
US/Pacific timezone

Next Generation RISC-V Interrupt Support

21 Sep 2021, 07:45
30m
Microconference3/Virtual-Room (LPC Virtual)

Microconference3/Virtual-Room

LPC Virtual

150
RISC-V MC RISC-V MC

Speaker

Anup Patel (Western Digital)

Description

The RISC-V Advanced Interrupt Architecture (RISC-V AIA) and RISC-V Advanced CLINT (RISC-V ACLINT) are non-ISA specifications which define next generation interrupt controller, timer, and inter-processor interrupt (IPI) devices for RISC-V platforms. The RISC-V AIA and ACLINT devices will support wired interrupts, message signaled interrupts (MSIs), virtualized message signaled interrupts (virtual MSIs), flexible machine-level timer, machine-level IPIs, and supervisor-level IPIs.

Both RISC-V AIA and ACLINT specifications are in final stages for being ratified and have been validated using QEMU, OpenSBI, Linux RISC-V, and Linux RISC-V KVM. This talk will involve an overview of RISC-V AIA and ACLINT specifications, detailed software status, and open items.

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Primary author

Anup Patel (Western Digital)

Presentation Materials